1. Field of the Invention
The present invention relates to a register circuit used in a synchronous integrated circuit that adopts clock gating, and especially relates to techniques for improving an operating frequency of the synchronous integrated circuit.
2. Related Art
Clock gating (also referred to as “gated clock”) is one of the techniques used for reducing power consumption of an integrated circuit.
To save power, clock gating stops supply of a clock signal to a circuit which is not operating, among a plurality of circuits that constitute the integrated circuit.
Conventional clock gating techniques typically use a logic cell, such as an AND circuit or an OR circuit, to control supply of a clock signal to a circuit. Such a logic cell used for clock gating is hereafter called a gated cell.
A conventional synchronous integrated circuit having a gated cell is described below.
FIG. 10 schematically shows a conventional synchronous integrated circuit 100 having a gated cell.
In the drawing, the synchronous integrated circuit 100 includes a register 101 that is subjected to clock signal supply control, an AND circuit 102 as a gated cell, registers 103 and 104, combinational circuits 105 and 106, a clock signal generation circuit 107, and buffers 111 and 112.
The clock signal generation circuit 107 outputs clock signal clk0, which is fed to the AND circuit 102 and the buffers 111 and 112 via a clock signal line 110.
The buffer 111 receives clock signal clk0, and outputs clock signal clk3 to the register 104.
The buffer 112 receives clock signal clk0, and outputs clock signal clk2 to the register 103.
The combinational circuit 105 outputs data signal data, which is fed to the register 101 via a data signal line 108.
The combinational circuit 106 outputs control signal en used for controlling supply of a clock signal to the register 101. Control signal en is fed to the AND circuit 102 via a control signal line 109.
The AND circuit 102 receives control signal en and clock signal clk0, and outputs clock signal clk1. FIG. 12 is a circuit diagram of the AND circuit 102.
The AND circuit 102 has a phase delay of time Tg between the signal input and the signal output.
The registers 101, 103, and 104 are each a master-slave flip-flop circuit.
FIG. 13 is a circuit diagram of the register 101.
The register 101 includes a passage control circuit 101a and a holding circuit 101b that constitute a master latch circuit, a passage control circuit 101c and a holding circuit 101d that constitute a slave latch circuit, and a clock signal inverter circuit 101e. The register 101 receives data signal data and clock signal clk1, and outputs latched data signal Q.
FIG. 11 is a timing chart of each signal at points A, B, C, D, X, and Y shown in FIG. 10.
In detail, clock signal clk1 is detected at point A, clock signal clk2 at point B, clock signal clk3 at point C, data signal data at point D, clock signal clk0 at point X, and control signal en at point Y.
As shown in FIG. 11, clock signals clk1, clk2, and clk3 detected respectively at points A, B, and C are in phase with each other.
There is a phase delay of time Tg between the input of clock signal clk0 to the AND circuit 102 and the output of clock signal clk1 from the AND circuit 102. Which is to say, clock signal clk0 leads in phase clock signal clk1 by delay time Tg. This being so, clock skew is adjusted by inserting the buffers 111 and 112 in branch lines of the clock signal line 110 so as to bring clock signals clk1, clk2, and clk3 input respectively to the registers 101, 103, and 104 into phase with each other.
Data signal data is set so that the beginning 1100 of data to be latched in the register 101 reaches the register 101 at least setup time Tsetup before a leading edge 1101 of clock signal clk1 input to the register 101.
Also, control signal en is set so that its trailing edge 1103 reaches the AND circuit 102 at least setup time Tsetup1 before a leading edge 1102 of clock signal clk0, in order to prevent clock signal clk1 from becoming high with the leading edge 1102 of clock signal clk0.
Clock cycle Tcycle is determined in accordance with a delay of a critical path, i.e. a path between registers that has a largest delay, in the synchronous integrated circuit 100.
A delay of a path between registers is a sum total of a wire propagation delay, an input/output delay of each circuit located between the registers, and a setup time of each circuit located between the registers. For example, a delay of a path between the registers 104 and 101 is Ten+Tsetup1+Tg, where Ten denotes a delay time of control signal en (wire propagation delay).
In the synchronous integrated circuit 100, the path between the registers 104 and 101 can be assumed to be the critical path. This being the case, clock cycle Tcycle is set so that Tcycle≧Ten+Tsetup1+Tg. This means if Ten+Tsetup1+Tg is smaller, clock cycle Tcycle can be reduced, with it being possible to improve an operating frequency of the synchronous integrated circuit 100.